1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method therefor, and more particularly to a structure of a capacitor with a desired capacitance on a miniaturized memory cell and a manufacturing method therefor.
2. Description of Related Art
In a semiconductor memory device (Dynamic Random Access Memory, hereinafter referred to as “DRAM”) which allows writing and reading as needed, one capacitor is connected with one transistor to retain charges. With recent technological development, there has become commercially practical a semiconductor memory device using a capacitor of a three-dimensional structure, among semiconductor memory devices such as, especially, a DRAM. For example, a conventional semiconductor memory device illustrated in FIGS. 11 and 12 of Japanese Patent Application Laid-Open No. 2000-156479 uses a cylindrical-type capacitor structure. For high integration degree, the conventional semiconductor memory device increases height size for required storage capacitance while reducing the occupying area of capacitors, using capacitors of such a three-dimensional structure.
Japanese Patent Application Laid-Open No. 2003-197771 has disclosed a capacitor structure obtainable of forming a lower electrode including a columnar portion, a sleeve portion isolatingly formed outside the columnar portion, and a connection portion for connecting the columnar portion lower end with the sleeve portion lower end, and then forming an upper electrode through a capacitor dielectric. This configuration provides a semiconductor device of a smaller cell area than the conventional one and a stable capacitor structure.
Japanese Patent Application Laid-Open No. 2003-234245 has disclosed capacitors of multilayer structure which has attained miniaturization and high capacitance. In the multilayer structure, a plurality of electrode layers forming a first electrode and a plurality of electrode layers forming a second electrode are alternately laminated via a dielectric layer by a thin film forming technique and the electrode layers forming the first electrode are connected with each other at one end portion without dielectric layers and the electrode layers forming the second electrode are connected with each other at the other end portion to construct a capacitor.
With miniaturization of elements, capacitors with high aspect ratio such as cylinder type, crown type or pillar type capacitors have been used. However, further development of miniaturization requires formation of a capacitor with desired capacitance on a memory cell of smaller size and therefore the mechanical strength of such a structure will be lowered and the difficulty in performing microfabrication such as dry etching has become high and hence it has become difficult to ensure a sufficient storage capacitance.
In the method of Japanese Patent Application Laid-Open No. 2003-197771, it will be caused a problem on the strength of a sleeve portion like a crown-type capacitor with further miniaturization. Japanese Patent Application Laid-Open No. 2003-234245 has not made effective use of height direction nor provided reduction of the area enough to be connected to a fine DRAM cell transistor, thus causing a problem with insufficient element miniaturization.
Furthermore, a DRAM requires formation of a peripheral circuit region as well as a memory cell region in which cell transistors are formed in an array manner. With higher miniaturization of the memory cell region, process sharing with the peripheral circuit region has become difficult more and more.
Accordingly, there has been demanded a semiconductor device with capacitors which have excellent mechanical strength and are easy to microfabricate even as element miniaturization has become higher and ensure sufficient storage capacitance.
Further, there has been demanded a semiconductor device which can share processes for forming various types of components in the peripheral circuit region and components in the memory cell region to solve the foregoing problems.